Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, and Flash. Similarly, spin-transfer (spin torque) magnetization switching described by C. Slonczewski in “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996), has recently stimulated considerable interest due to its potential application for spintronic devices such as STT-RAM on a gigabit scale.
Both MRAM and STT-RAM have a MTJ element based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. The MTJ element is typically formed between a bottom electrode such as a first conductive line and a top electrode which is a second conductive line at locations where the top electrode crosses over the bottom electrode. A MTJ stack of layers may have a bottom spin valve configuration in which a seed layer, an anti-ferromagnetic (AFM) pinning layer, a ferromagnetic “pinned” layer, a thin tunnel barrier layer, a ferromagnetic “free” layer, and a capping layer are sequentially formed on a bottom electrode. The AFM layer holds the magnetic moment of the pinned layer in a fixed direction. The pinned layer has a magnetic moment that is fixed in the “y” direction, for example, by exchange coupling with the adjacent AFM layer that is also magnetized in the “y” direction. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
In a read operation, the information stored in a MRAM cell is read by sensing the magnetic state (resistance level) of the MTJ element through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the MRAM cell by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. One line (bit line) provides the field parallel to the easy axis of the bit while another line (digit line) provides the perpendicular (hard axis) component of the field. The intersection of the lines generates a peak field that is engineered to be just over the switching threshold of the MTJ.
A high performance MRAM MTJ element is characterized by a high tunneling magnetoresistive (TMR) ratio which is dR/R where R is the minimum resistance of the MTJ element and dR is the change in resistance observed by changing the magnetic state of the free layer. A high TMR ratio and resistance uniformity (Rp_cov), and a low switching field (Hc) and low magnetostriction (λS) value are desirable for conventional MRAM applications. For Spin-RAM (STT-RAM), a high λS and high Hc leads to high anisotropy for greater thermal stability. This result is accomplished by (a) well controlled magnetization and switching of the free layer, (b) well controlled magnetization of a pinned layer that has a large exchange field and high thermal stability and, (c) integrity of the tunnel barrier layer. In order to achieve good barrier properties such as a specific junction resistance x area (RA) value and a high breakdown voltage (Vb), it is necessary to have a uniform tunnel barrier layer which is free of pinholes that is promoted by a smooth and densely packed growth in the AFM and pinned layers. RA should be relatively small (about 4000 ohm-μm2 or less) for MTJs that have an area defined by an easy axis and hard axis dimensions of less than 1 micron. Otherwise, R would be too high to match the resistance of the transistor which is connected to the MTJ.
As the size of MRAM cells decreases, the use of external magnetic fields generated by current carrying lines to switch the magnetic moment direction becomes problematic. One of the keys to manufacturability of ultra-high density MRAMs is to provide a robust magnetic switching margin by eliminating the half-select disturb issue. For this reason, a new type of device called a spin transfer (spin torque) device was developed. Compared with conventional MRAM, spin-transfer torque or STT-RAM has an advantage in avoiding the half select problem and writing disturbance between adjacent cells. The spin-transfer effect arises from the spin dependent electron transport properties of ferromagnetic-spacer-ferromagnetic multilayers. When a spin-polarized current transverses a magnetic multilayer in a CPP configuration, the spin angular moment of electrons incident on a ferromagnetic layer interacts with magnetic moments of the ferromagnetic layer near the interface between the ferromagnetic and non-magnetic spacer. Through this interaction, the electrons transfer a portion of their angular momentum to the ferromagnetic layer. As a result, spin-polarized current can switch the magnetization direction of the ferromagnetic layer if the current density is sufficiently high, and if the dimensions of the multilayer are small. The difference between a STT-RAM and a conventional MRAM is only in the write operation mechanism. The read mechanism is the same.
In order for STT-RAM to be viable in the 90 nm technology node and beyond, MTJs must exhibit a TMR ratio that is much higher than in a conventional MRAM-MTJ which uses AlOx as the tunnel barrier and a NiFe free layer. Furthermore, the critical current density (Jc) must be lower than 106 A/cm2 to be driven by a CMOS transistor that can typically deliver 100 μA per 100 nm gate width. A critical current for spin transfer switching (Ic), which is defined as [(Ic++Ic−I)/2], for the present 180 nm node sub-micron MTJ having a top-down area of about 0.2×0.4 micron, is generally a few milliamperes. The critical current density (Jc), for example (Ic/A), is on the order of several 107 A/cm2. This high current density, which is required to induce the spin-transfer effect, could destroy a thin tunnel barrier made of AlOx, MgOx, or the like. Thus, for high density devices such as STT-RAM on a gigabit scale, it is desirable to decrease Ic (and its Jc) by more than an order of magnitude so as to avoid an electrical breakdown of the MTJ device and to be compatible with the underlying CMOS transistor that is used to provide switching current and to select a memory cell.
Once a certain MTJ cell has been written to, the circuits must be able to detect whether the MTJ is in a high or low resistance state which is called the “read” process. Uniformity of the TMR ratio and the absolute resistance of the MTJ cell are critical in MRAM (and STT-RAM) architecture since the absolute value of MTJ resistance is compared with a reference cell in a fixed resistance state during read mode. Needless to say, the read process introduces some statistical difficulties associated with the variation of resistances of MTJ cells within an array. If the active device resistances in a block of memory show a large resistance variation (i.e. high Rp_cov, Rap_cov), a signal error can occur when they are compared with a reference cell. In order to have a good read operation margin, TMR/Rp_cov (or Rap_cov) should have a minima of 12, preferably >15, and most preferably >20 where Rp is the MTJ resistance for free layer magnetization aligned parallel to pinned layer magnetization (which is fixed) and Rap is the resistance of free layer magnetization aligned anti-parallel to the pinned layer magnetization.
The intrinsic critical current density (Jc) as given by Slonczewski of IBM is shown in the following equation (1):Jc=2eαMstF(Ha+Hk+2πMs)/hη  (1)where e is the electron charge, α is a Gilbert damping constant, tF is the thickness of the free layer, h is the reduced Plank's constant, η is the spin-transfer efficiency which is related to the spin polarization (P), Ha is the external applied field, and Hk is the uniaxial anisotropy field, and 2π Ms is the demagnetization field of the free layer.
Normally, the demagnetizing field, 2πMs (several thousand Oe term) is much larger than the uniaxial anisotropy field Hk and external applied field (about 100 Oe) Ha term, hence the effect of Hk and Ha on Jc are small. In equation (2), V equals MS(tFA) and is the magnetic volume which is related to the thermal stability function term KuV/kbT where Ku is the magnetic anisotropy energy and kb is the Boltzmann constant.Jc∝αMsV/hη  (2)
Referring to FIG. 1, a STT-RAM structure 1 is shown and includes a gate 5 formed above a p-type semiconductor substrate 2, a source 3, drain 4, word line (WL) 6, bottom electrode (BE) 7, and bit line (BL) 9. There is also a MTJ element 8 formed between the bit line 9 and bottom electrode 7, and a via 10 for connecting the BE to the drain 4.
Another publication relating to a STT-RAM (Spin-RAM) structure is by M. Hosomi et al. in “A novel non-volatile memory with spin torque transfer magnetization switching: Spin-RAM”, 2005 IEDM, paper 19-1, and describes a 4 Kbit Spin RAM having CoFeB pinned and free layers, and a RF-sputtered MgO tunnel barrier that was annealed under 350° C. and 10000 Oe conditions. The MTJ size is 100 nm×150 nm in an oval shape. The tunnel barrier is made of crystallized (001) MgO with a thickness controlled to <10 Angstroms for a proper RA of around 20 ohm-μm2. Intrinsic dR/R of the MTJ stack is 160% although dR/R for the 100 nm×150 nm bit during read operation (with 0.1 V bias) is about 90% to 100%. Using a 10 ns pulse width, the critical current density, Jc, for spin transfer magnetization switching is around 2.5×106 A/cm2. Write voltage distribution on a 4 Kbit circuit for high resistance state to low resistance (P to AP) and low resistance state to high resistance state (AP to P) has shown good write margin. Resistance distribution for the low resistance state (Rp) and high resistance state (Rap) has a sigma (Rp_cov) of about 4%. Thus, for a read operation, TMR (with 0.1 V bias)/Rp_cov is >20.
J. Hayakawa et al. in “Current Driven Magnetization Switch in CoFeB/MgO/CoFeB Magnetic Tunnel Junctions”, Japan J. Appl. Phys., Vol. 41, p. 1267 (2005), report a Jc (10 ns pulse width) of ˜2.5×106 A/cm2 for a MTJ processed with 350° C. annealing and having a MgO tunnel barrier which results in a RA of about 10 ohm-cm2 and a MR (intrinsic) of around 160%. J. Hayakawa et al. in “Current-induced magnetization switching in MgO barrier based magnetic tunnel junctions with CoFeB/Ru/CoFeB synthetic ferromagnetic free layer”, j-hayakawa@rd.hitachi.co.jp, report a Jc0 of 8.9×106 A/cm2 for a 80 nm×160 nm oval shaped MTJ processed with 300° C. annealing which results in dR/R=90% and a thermal stability factor E/kBT>60.
A 2 Mb spin-transfer torque RAM (SPRAM) was described by T. Kawahara et al. in “2 Mb spin-transfer torque RAM with bit-by-bit bidirectional current write and parallelizing-direction current read”, 2007 IEEE International Solid State Circuits Conference, and has a CoFe(B)/MgO/CoFe—NiFe MTJ (100 nm×50 nm oval shape) with a switching voltage by quasistatic measurement of about 0.7 V and a Jc0 estimated to be >2.5×106 A/cm2.
Y. Huai et al. in “Spin transfer switching current reduction in magnetic tunnel junction based dual spin filter structures”, Appl. Phys. Lett. V 87, p 222510(2005), report that a dual spin filter (DSF) shows that a second pinned layer creates additional spin transfer torque which helps to switch free layer magnetization. The Jc0 value is reduced by a factor of 3× to ˜2.2×106 A/cm2.
Z. Diao et al. in “Spin transfer switching in dual MgO magnetic tunnel junctions”, APL, Vol. 90, pp. 132508 (2007) demonstrated that although a DSF structure reduces Jc0 by a factor of 2× compared with a single spin valve, the dR/R suffers by decreasing to about one half the value of a conventional MTJ.
H. Meng and J. Wang in “Composite free layer for high density magnetic random access memory with low spin transfer current”, APL Vol. 89, pp. 152509 (2006), show that a composite free layer with a nanocurrent (NCC) FeSiO layer sandwiched between two CoFe layers is capable of reducing Jc0 to 8×106 A/cm2 from 2.4×107 A/cm2 for a MTJ with a CoFe free layer.
In summary, the prior art suggests that (a) Jc0>2×106 A/cm2 for a conventional MgO-MTJ fabricated with a single “barrier” layer; (b) there is a >2× reduction in Jc0 for a dual spin filter MTJ having two anti-parallel pinned layers; (c) a MTJ fabricated with a NCC free layer can achieve considerably lower Jc0; and (d) dR/R (MR) of a DSF MTJ or a NCC free layer containing MTJ is reduced considerably so that read operational margin of the devices is too small to satisfy the STT-RAM product requirements. For example, in advanced STT-RAM devices having a 1 Gbit density and a 100 nm×150 nm oval size MTJ, Rp_cov is typically about 5% which means dR/R must be at least 100% in order to achieve the desired TMR/Rp_cov ratio of ≧20. Therefore, further improvement in STT-RAM technology is necessary before a viable product based on the 90 nm technology node is achieved. In particular, a combination of a high TMR ratio, TMR/Rp_cov ratio >20, and a low Jc of less than 2×106 A/cm2 is needed.
U.S. Patent Application No. 2007/0085068 teaches a MTJ with a composite free layer switched by spin transfer and comprised of at least one layer of CoFeB and a granular layer having grains in a matrix. The granular layer may be represented by TMyOxide(100-y) where TM is one of Ni, Fe, and Co, and the oxide includes at least one of AlOx, SiOx, TiOx, TaOx, ZrOx, HfOx, MgO, and y is between 5 and 50 atomic %.
In U.S. Patent Application No. 2007/0171694, one or more spin diffusion layers are disposed next to the free layer and outside a structure formed by the pinned layer, free layer, and middle layer between the free and pinned layers. A spin diffusion layer is employed to reduce the spin transfer switching current.
U.S. Pat. No. 7,180,713 teaches a granular structure layer formed in a free layer in which the conductive particles are made of a magnetic metal material thereby reducing the sense current path so that the element output can be increased.